The present invention generally relates to semiconductor process integration, and more specifically relates to a semiconductor device which has Sixe2x80x94Ge on Silicon, and a method of making a semiconductor device where the method includes depositing Sixe2x80x94Ge on Silicon.
The semiconductor industry has been constantly striving to improve the performance of semiconductor devices (i.e., semiconductor products). To date, various schemes and improvements have been proposed, both in the area of process technology and circuit design, in order to improve speed, reduce power consumption, or otherwise improve performance.
Present semiconductor devices are typically configured such that FET transistors and other devices, such as speed-performance sensitive parts of a circuit, are disposed on Silicon. The scaling of transistors to smaller dimensions for reduced die size, increased logic functionality and reduced power has resulted in a decrease in the operational performance of a transistor. The drop in transistor drive currents reduces the performance of a circuit and increases the dynamic power consumption. The reduction in the drive current results from a decrease in the mobility of the electron due to increased surface and impurity scattering in the surface channel of the device.
A general object of an embodiment of the present invention is to provide a semiconductor device which has at least a region that provides Sixe2x80x94Ge on Silicon.
Another object of an embodiment of the present invention is to provide a method of making a semiconductor device, where the method includes depositing Sixe2x80x94Ge on Silicon.
Still another object of an embodiment of the present invention is to provide a semiconductor device which is configured such that carrier flow is confined or near the surface of the device.
Still yet another object of an embodiment of the present invention is to provide a semiconductor device which is configured such that it reduces leakage and power consumption.
Yet still another object of an embodiment of the present invention is to provide a semiconductor device which is configured such that electron hole carrier mobility is improved, thereby resulting in improved transistor performance.
Briefly, and in accordance with at least one of the forgoing objects, an embodiment of the present invention provides a semiconductor device which has at least a region where Sixe2x80x94Ge is disposed on Silicon. Specifically, the semiconductor device preferably includes Sixe2x80x94Ge disposed on a Silicon substrate. The semiconductor device may include a Silicon region which does not include any Sixe2x80x94Ge, but preferably also includes an Sixe2x80x94Ge region which includes Sixe2x80x94Ge on Silicon. While the Silicon region includes a thermal oxide layer, the Sixe2x80x94Ge region does not. Preferably, the Sixe2x80x94Ge is provided as an Sixe2x80x94Ge layer which is disposed between a Silicon layer and the Silicon substrate. Ideally, there is at least one circuit device or circuitry on the Silicon region and at least one circuit device or circuitry on the Sixe2x80x94Ge region. The lattice structure in the silicon layer grown above the Sixe2x80x94Ge layer is strained due to the lattice mismatch between the epitaxial Sixe2x80x94Ge and Si regions. This strained silicon layer results in less electron scattering, which improves electron mobility and results in improved transistor switching speed and lower dynamic power consumption. These layers of Germanium doped silicon and Strained silicon do not have to be selectively grown on the surface of the exposed substrate. These films can be grown on the surface of the exposed substrate and at the same time depositing a poly crystalline version of the film on the surface above the silicon dioxide layers. The thickness of these poly crystalline layers can be thinner or thicker than the epitaxial grown layers.
A method of making such a semiconductor device is also provided, and includes steps of forming a thermal oxide layer on a Silicon substrate, masking at least a portion of the thermal oxide layer, removing (such as by wet etching) at least a portion of the thermal oxide layer in order to expose a portion of the Silicon substrate, epitaxially growing an Sixe2x80x94Ge layer selectively on the exposed portion of the Silicon substrate using either undoped Sixe2x80x94Ge or Sixe2x80x94Ge doped with carbon, epitaxially growing a Silicon layer on the Sixe2x80x94Ge layer using either undoped Silicon or Silicon doped with nitrogen, and continuing manufacture of the device by forming a circuit on the Sixe2x80x94Ge regions and non-Sixe2x80x94Ge regions of the semiconductor device.